In the present era of very large scale integration, new techniques are needed to more efficiently utilize the space within the semiconductor devices. Certain practical limitations, however, in today's manufacturing process of semiconductors require portions of semiconductor material to be used merely for providing spacing to compensate for such limitations. Such use of semiconductor material occurs in the process of providing interconnecting contacts for the semiconductor devices.
In the manufacture of integrated circuits, interconnecting contacts are provided between the active semiconductive material in which the semiconductor devices are formed, and the interconnect lines. These contacts are typically formed by initially depositing an oxide layer over the top surface of the semiconductor device. A masking layer of photoresist is then provided over the oxide and patterned for exposing the oxide in the contact area. The exposed oxide is then etched, followed by the nonselective deposition of a conducting layer such as aluminum, over the wafer. The conducting layer is then patterned and etched to form the interconnecting contacts.
Inherent in the masking step for patterning the contact areas is the high probability of misaligning the masking layer over the oxide. This misalignment of the masking layer leads to the misalignment of the interconnecting contacts. Additionally, there exists the potential of overetching the oxide layer during the etching process, which can result in enlarging the size of the contact areas. Either of these occurrences, e.g., the misalignment of the mask or the overetching of the oxide, can short the contacts for the active device regions with the gate of the semiconductor. To avoid this potential for shorting the gate, extra semiconductor material of approximately 2 microns in width is typically provided on each side of the intended location for the contacts such that any potentially misaligned or enlarged contact will be prevented from shorting the active regions with the gate. This usage of unused active semiconductor area, however, is a loss of valuable semiconductor real estate which might otherwise be used for additional semiconductor devices.